View MAX9171ETA_5229493.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max9171/max9172 single/dual low-voltage differential signaling (lvds) receivers are designed for high-speed applications requiring minimum power consumption, space, and noise. both devices support switching rates exceeding 500mbps while operating from a single 3.3v supply. the max9171 is a single lvds receiver and the max9172 is a dual lvds receiver. both devices con- form to the ansi tia/eia-644 lvds standard and con- vert lvds to lvttl/lvcmos-compatible outputs. a fail-safe feature sets the outputs high when the inputs are undriven and open, terminated, or shorted. the max9171/max9172 are available in 8-pin so packages and space-saving thin dfn and sot23 packages. for lower skew devices, refer to the max9111/ max9113 data sheet. applications multipoint backplane interconnect laser printers digital copiers cellular phone base stations lcd displays network switches/routers clock distribution features input accepts lvds and lvpecl in-path fail-safe circuit space-saving 8-pin tdfn and sot23 packages fail-safe circuitry sets output high for open, undriven shorted, or undriven terminated output flow-through pinout simplifies pcb layout guaranteed 500mbps data rate second source to ds90lv018a and ds90lv028a (so packages only) conforms to ansi tia/eia-644 standard 3.3v supply voltage -40? to +85? operating temperature range low-power dissipation max9171/max9172 single/dual lvds line receivers with ?n-path?fail-safe ________________________________________________________________ maxim integrated products 1 ordering information 19-2578; rev 2; 6/07 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part pin-package top mark pkg code max9171 eka-t 8 sot23-8 aalx k8-1 max9171esa 8 so s8-2 MAX9171ETA* 8 thin dfn-ep** t833-2 max9172 eka-t 8 sot23-8 aaly k8-1 max9172esa 8 so s8-2 max9172eta* 8 thin dfn-ep** t833-2 1 2 3 4 5 6 7 8 so/tdfn* in- in+ n.c. n.c. gnd n.c. out v cc in- in+ n.c. n.c. gnd n.c. out v cc in1- in1+ in2+ in2- gnd out2 out1 v cc in1- in1+ in2- out2 gnd in2+ out1 v cc max9171 1 2 3 4 5 6 7 8 so/tdfn* max9172 1 2 3 4 5 6 7 8 sot23 max9172 1 2 3 4 8 7 6 5 sot23 max9171 pin configurations note: all devices are specified over the -40c to +85? operating temperature range. * future product?ontact factory for availability. ** ep = exposed pad. t = tape-and-reel.
max9171/max9172 single/dual lvds line receivers with ?n-path?fail-safe 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = 3.0v to 3.6v, differential input voltage |v id | = 0.1v to 1.2v, receiver input voltage = 0 to v cc , common-mode voltage v cm = |v id /2| to (v cc - |v id /2|), t a = -40? to +85?, unless otherwise noted. typical values are at v cc = 3.3v, |v id | = 0.2v, v cm = 1.2v, t a = +25?.) (notes 1, 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ...........................................................-0.3v to +4.0v in_+, in_- to gnd .................................................-0.3v to +4.0v out_ to gnd ............................................-0.3v to (v cc + 0.3v) continuous power dissipation (t a = +70?) 8-pin sot23 (derate 8.9mw/? above +70?) ...........714mw 8-pin so (derate 5.9mw/? above +70?) .................471mw 8-pin tdfn (derate 24.4mw/? above +70?) ........1951mw operating temperature range ..........................-40? to +85? junction temperature .....................................................+150? storage temperature range ............................-65? to +150? esd protection human body model (in_+, in_-) ...................................?3kv lead temperature (soldering, 10s) ................................+300? parameter symbol conditions min typ max units lvds inputs (in_+, in_-) differential input high threshold v th figure 1 -40 0 mv differential input low threshold v tl figure 1 -100 -40 mv input current (noninverting input) i in+ figure 1 +0.5 -2.1 -5.0 a power-off input current (noninverting input) i in+off v in+ = 0 to 3.6v, v in- = 0 to 3.6v, v cc = 0 or open (figure 1) -0.5 0 +0.5 a input current (inverting input) i in- figure 1 -0.5 +4.4 +10.0 a power-off input current (inverting input) i in-off v in+ = 0 to 3.6v, v in- = 0 to 3.6v, v cc = 0 or open (figure 1) -0.5 0 +0.5 a lvcmos/lvttl outputs (out_) open, undriven short, or undriven parallel termination 2.7 3.2 output high voltage v oh i oh = -4.0ma v id = 0v 2.7 3.2 v output low voltage v ol i ol = 4.0ma, v id = -100mv 0.1 0.4 v output short-circuit current i os v out_ = 0 (note 3) -45 -77 -120 ma power supply max9171 3.6 6 supply current i cc inputs open max9172 7.0 9 ma
max9171/max9172 single/dual lvds line receivers with ?n-path?fail-safe _______________________________________________________________________________________ 3 note 1: current into a pin is defined as positive. current out of a pin is defined as negative. all voltages are referenced to gnd except v th , v tl , and v id . note 2: all devices are 100% production tested at t a = +25 c and are guaranteed by design for t a = -40 c to +85 c, as specified. note 3: short only one output at a time. do not exceed the absolute maximum junction temperature specification. note 4: ac parameters are guaranteed by design and not production tested. note 5: c l includes scope probe and test jig capacitance. note 6: pulse generator output conditions: t r = t f < 1ns (0% to 100%), frequency = 250mhz, 50% duty cycle, v oh = 1.3v, v ol = 1.1v. note 7: t skd1 is the magnitude of the difference of differential propagation delays in a channel. t skd1 = |t phld - t plhd |. note 8: t skd2 is the magnitude of the difference of the t plhd or t phld of one channel and the t plhd or t phld of the other channel on the same part. note 9: t skd3 is the magnitude of the difference of any differential propagation delays between parts at the same v cc and within 5 c of each other. note 10: t skd4 is the magnitude of the difference of any differential propagation delays between parts operating over the rated supply and temperature ranges. switching characteristics (v cc = 3.0v to 3.6v, c l = 15pf, |v id | = 0.2v, v cm = 1.2v, t a = -40 c to +85 c, unless otherwise noted. typical values are at v cc = 3.3v, t a = +25 c.) (notes 4, 5, 6) parameter symbol conditions min typ max units differential propagation delay high to low t phld figures 2, 3 1.0 1.65 2.5 ns differential propagation delay low to high t plhd figures 2, 3 1.0 1.62 2.5 ns differential pulse skew |t phld - t plhd | t skd1 figures 2, 3 (note 7) 30 400 ps differential channel-to-channel skew (max9172) t skd2 figures 2, 3 (note 8) 40 500 ps t skd3 figures 2, 3 (note 9) 1 differential part-to-part skew t skd4 figures 2, 3 (note 10) 1.5 ns rise time t tlh figures 2, 3 0.55 0.8 ns fall time t thl figures 2, 3 0.51 0.8 ns maximum operating frequency f max all channels switching, v ol(max) = 0.4v, v oh(min) = 2.7v, 40% < duty cycle < 60% 250 300 mhz
max9171/max9172 single/dual lvds line receivers with ?n-path?fail-safe 4 _______________________________________________________________________________________ typical operating characteristics (v cc = 3.3v, v cm = 1.2v, |v id | = 0.2v, f in = 200mhz, c l = 15pf, t a = +25 c, unless otherwise specified.) output high voltage vs. supply voltage max9171 toc01 supply voltage (v) output high voltage (v) 3.5 3.4 3.3 3.2 3.1 3.0 3.1 3.2 3.3 3.4 3.5 3.6 2.9 3.0 3.6 i oh = -4ma output low voltage vs. supply voltage max9171 toc02 supply voltage (v) output low voltage (mv) 3.5 3.4 3.3 3.2 3.1 85 90 95 100 80 3.0 3.6 i ol = +4ma output short-circuit current vs. supply voltage max9171 toc03 supply voltage (v) output short-circuit current (ma) 3.5 3.4 3.3 3.2 3.1 -80 -75 -70 -65 -85 3.0 3.6 v id = +200mv, output shorted to ground differential threshold voltage vs. supply voltage max9171 toc04 supply voltage (v) differential threshold voltage (mv) 3.5 3.4 3.3 3.2 3.1 -50 -45 -40 -35 -55 3.0 3.6 high-low low-high max9172 supply current vs. frequency max9171 toc05 frequency (mhz) supply current (ma) 100 10 1 10 20 30 40 0 0.1 1000 both channels switching one channel switching max9172 supply current vs. temperature max9171 toc06 temperature ( c) supply current (ma) 60 35 10 -15 7 8 9 6 -40 85 f = 1mhz both channels switching differential propagation delay vs. supply voltage max9171 toc07 supply voltage (v) differential propagation delay (ns) 3.5 3.4 3.3 3.2 3.1 1.5 2.0 2.5 1.0 3.0 3.6 t phld t plhd differential propagation delay vs. temperature max9171 toc08 temperature ( c) differential propagation delay (ns) 60 35 10 -15 1.6 1.7 1.8 1.9 2.0 1.5 -40 85 t phld t plhd
max9171/max9172 single/dual lvds line receivers with ?n-path?fail-safe _______________________________________________________________________________________ 5 differential pulse skew vs. supply voltage max9171 toc09 supply voltage (v) differential pulse skew (ps) 3.5 3.4 3.3 3.2 3.1 30 60 90 120 0 3.0 3.6 differential pulse skew vs. temperature max9171 toc10 temperature ( c) differential pulse skew (ps) 60 35 10 -15 40 80 120 160 200 0 -40 85 differential propagation delay vs. differential input voltage max9171 toc11 differential input voltage (mv) differential propagation delay (ns) 2100 1600 1100 600 1.5 2.0 2.5 3.0 1.0 100 2600 f in = 20mhz t phld t plhd differential propagation delay vs. common-mode voltage max9171 toc12 common-mode voltage (v) differential propagation delay (ns) 2.6 2.1 1.6 1.1 0.6 1.3 1.6 1.9 2.2 2.5 1.0 0.1 3.1 f in = 20mhz t phld t plhd transition time vs. temperature max9171 toc13 temperature ( c) transition time (ps) 60 35 10 -15 400 500 600 700 300 -40 85 t tlh t thl differential propagation delay vs. load max9171 toc14 load (pf) differential propagation delay (ns) 40 30 20 1.6 1.8 2.0 2.2 2.4 1.4 10 50 f in = 20mhz t phld t plhd transition time vs. load max9171 toc15 load (pf) transition time (ps) 40 30 20 500 900 1300 1700 2100 100 10 50 t tlh t thl differential pulse skew vs. input transition time max9171 toc16 input transition time (ns) differential pulse skew (ps) 2.5 2.0 1.5 50 100 150 200 250 300 0 1.0 3.0 typical operating characteristics (continued) (v cc = 3.3v, v cm = 1.2v, |v id | = 0.2v, f in = 200mhz, c l = 15pf, t a = +25 c, unless otherwise specified.)
max9171/max9172 detailed description lvds inputs the max9171/max9172 feature lvds inputs for inter- facing high-speed digital circuitry. the lvds interface standard is a signaling method intended for point-to- point communication over controlled-impedance media, as defined by the ansi tia/eia-644 standards. the technology uses low-voltage signals to achieve fast transition times and minimize power dissipation and noise immunity. the max9171/max9172 convert lvds signals to lvcmos/lvttl signals at rates in excess of 500mbps. these devices are capable of detecting dif- ferential signals as low as 100mv and as high as 1.2v within a 0 to v cc input voltage range. table 1 is the input-output function table. fail-safe the max9171/max9172 fail-safe drives the receiver output high when the differential input is: open undriven and shorted undriven and terminated without fail-safe, differential noise at the input may switch the receiver and appear as data to the receiving system. an open input occurs when a cable and termi- nation are disconnected. an undriven, terminated input occurs when a cable is disconnected with the termina- tion still connected across the receiver inputs or when the driver of a receiver is in high impedance. an undriv- en, shorted input can occur due to a shorted cable. single/dual lvds line receivers with ?n-path?fail-safe 6 _______________________________________________________________________________________ max9171 pin description pin sot23 so/tdfn name function 18v cc positive power-supply input. bypass with a 0.1f and a 0.001f capacitor to gnd with the smallest capacitor closest to the pin. 2 5 gnd ground 3 7 out receiver output 4, 5, 6 3, 4, 6 n.c. no connection. not internally connected. 7 2 in+ noninverting differential receiver input 8 1 in- inverting differential receiver input ( td fn onl y) ep exposed paddle. solder to pcb ground. max9172 pin description pin sot23 so/tdfn name function 18v cc positive power-supply input. bypass with a 0.1f and a 0.001f capacitor to gnd with the smallest capacitor closest to the pin. 2 5 gnd ground 3 7 out1 receiver output 1 4 6 out2 receiver output 2 5 4 in2- inverting differential receiver input 2 6 3 in2+ noninverting differential receiver input 2 7 2 in1+ noninverting differential receiver input 1 8 1 in1- inverting differential receiver input 1 ( td fn onl y) ep exposed paddle. solder to pcb ground. inputs output (in_+) - (in_-) out_ 0mv high -100mv low open high undriven short high undriven parallel termination high table 1. input-output function table
in-path vs. parallel fail-safe the max9171/max9172 have in-path fail-safe that is compatible with in-path fail-safe receivers, such as the ds90lv018a and ds90lv028a. refer to the max9111/ max9113 data sheet for pin-compatible receivers with parallel fail-safe and lower jitter. refer to the max9130 data sheet for a single lvds receiver with parallel fail- safe in an sc70 package. the max9171/max9172 with in-path fail-safe are designed with a +40mv input offset voltage, a 2.5a current source between v cc and the noninverting input, and a 5a current sink between the inverting input and ground (figure 1). if the differential input is open, the 2.5a current source pulls the input to v cc - 0.7v and the 5a source sink pulls the inverting input to ground, which drives the receiver output high. if the dif- ferential input is shorted or terminated with a typical value termination resistor, the +40mv offset drives the receiver output high. if the input is terminated and float- ing, the receiver output is driven high by the +40mv off- set, and the 2:1 current sink to current source ratio (5a:2.5a) pulls the inputs to ground. this can be an advantage when switching between drivers on a multi- point bus because the change in common-mode volt- age from ground to the typical driver offset voltage of 1.2v is not as much as the change from v cc to 1.2v (parallel fail-safe pulls the bus to v cc ). figure 2 shows the propagation delay and transition test time circuit and figure 3 shows the propagation delay and transi- tion test time waveforms. max9171/max9172 single/dual lvds line receivers with ?n-path?fail-safe _______________________________________________________________________________________ 7 out_ v cc in_+ in_- 5 a 2.5 a 40mv figure 1. input with in-path fail-safe network equivalent circuit 50 ? 50 ? in_- out_ in_+ 15pf pulse generator figure 2. propagation delay and transition test time circuit in_+ in_- t plhd 20% 80% out_ v oh v ol 1.5v 1.5v 20% 80% 1.2v (0v differential) v id = 0.2v 1.3v 1.1v t phld t thl t tlh figure 3. propagation delay and transition time waveforms
max9171/max9172 esd protection esd protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. the receiver inputs of the max9171/max9172 have extra protection against static electricity. these pins are protected to 13kv without damage. the structures withstand esd during normal operation and when powered down. the receiver inputs of these devices are characterized for protection to the limit of 13kv using the human body model. human body model figure 4a shows the human body model, and figure 4b shows the current waveform it generates when dis- charged into a low-impedance load. this model con- sists of a 100pf capacitor charged to the esd test voltage, which is then discharged into the test device through a 1.5k ? resistor. applications information supply bypassing bypass v cc with high-frequency surface-mount ceram- ic 0.1f and 0.001f capacitors in parallel, as close to the device as possible, with the 0.001f capacitor clos- est to the device. for additional supply bypassing, place a 10f tantalum or ceramic capacitor at the point where power enters the circuit board. differential traces input trace characteristics affect the performance of the max9171/max9172. use controlled-impedance pcb traces to match the cable characteristic impedance. eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. reduce skew by matching the electrical length of traces. each channel s differential signals should be routed close to each other to cancel their external magnetic field. maintain a constant distance between the differ- ential traces to avoid discontinuities in differential impedance. avoid 90 turns and minimize the number of vias to further prevent impedance discontinuities. cables and connectors transmission media typically have a controlled differen- tial impedance of about 100 ? . use cables and connec- tors that have matched differential impedance to minimize impedance discontinuities. balanced cables tend to pick up noise as common mode, which is rejected by the lvds receiver. termination the max9171/max9172 require an external termination resistor. the termination resistor should match the differ- ential impedance of the transmission line. termin ation resistance values may range between 90 ? to 132 ? , depending on the characteristic impedance of the transmission medium. when using the max9171/max9172, minimize the dis- tance between the input termination resistors and the max9171/max9172 receiver inputs. use a single 1% surface-mount resistor. board layout for lvds applications, a four-layer pcb that provides separate power, ground, lvds signals, and output sig- nals is recommended. separate the input lvds signals from the output signals to prevent crosstalk. solder the exposed pad on the tdfn package to a pad connected to the pcb ground plane by a matrix of vias. connecting the exposed pad is not a substitute for connecting the ground pin. always connect pin 5 on the tdfn pack- age to ground. chip information transistor count: 624 process: cmos single/dual lvds line receivers with ?n-path?fail-safe 8 _______________________________________________________________________________________ charge-current limit resistor discharge resistance storage capacitor c s 100pf r c 1m ? r d 1500 ? high- voltage dc source device under test figure 4a. human body esd test modules i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing (not drawn to scale) i r 10% 0 0 amperes figure 4b. human body current waveform
max9171/max9172 single/dual lvds line receivers with ?n-path?fail-safe _______________________________________________________________________________________ 9 sot23, 8l .eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max9171/max9172 single/dual lvds line receivers with ?n-path?fail-safe 10 ______________________________________________________________________________________ package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) soicn .eps package outline, .150" soic 1 1 21-0041 b rev. document control no. approval proprietary information title: top view front view max 0.010 0.069 0.019 0.157 0.010 inches 0.150 0.007 e c dim 0.014 0.004 b a1 min 0.053 a 0.19 3.80 4.00 0.25 millimeters 0.10 0.35 1.35 min 0.49 0.25 max 1.75 0.050 0.016 l 0.40 1.27 0.394 0.386 d d min dim d inches max 9.80 10.00 millimeters min max 16 ac 0.337 0.344 ab 8.75 8.55 14 0.189 0.197 aa 5.00 4.80 8 n ms012 n side view h 0.244 0.228 5.80 6.20 e 0.050 bsc 1.27 bsc c h e e b a1 a d 0-8 l 1 variations:
max9171/max9172 single/dual lvds line receivers with ?n-path?fail-safe ______________________________________________________________________________________ 11 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 6, 8, &10l, dfn thin.eps
max9171/max9172 single/dual lvds line receivers with ?n-path?fail-safe maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) common dimensions symbol min. max. a 0.70 0.80 d 2.90 3.10 e 2.90 3.10 a1 0.00 0.05 l 0.20 0.40 pkg. code n d2 e2 e jedec spec b [(n/2)-1] x e package variations 0.25 min. k a2 0.20 ref. 2.00 ref 0.25 ? 0.05 0.50 bsc 2.30 ? 0.10 10 t1033-1 2.40 ref 0.20 ? 0.05 - - - - 0.40 bsc 1.70 ? 0.10 2.30 ? 0.10 14 t1433-1 1.50 ? 0.10 mo229 / weed-3 0.40 bsc - - - - 0.20 ? 0.05 2.40 ref t1433-2 14 2.30 ? 0.10 1.70 ? 0.10 t633-2 6 1.50 ? 0.10 2.30 ? 0.10 0.95 bsc mo229 / weea 0.40 ? 0.05 1.90 ref t833-2 8 1.50 ? 0.10 2.30 ? 0.10 0.65 bsc mo229 / weec 0.30 ? 0.05 1.95 ref t833-3 8 1.50 ? 0.10 2.30 ? 0.10 0.65 bsc mo229 / weec 0.30 ? 0.05 1.95 ref 2.30 ? 0.10 mo229 / weed-3 2.00 ref 0.25 ? 0.05 0.50 bsc 1.50 ? 0.10 10 t1033-2 revision history pages changed at rev 2: 1, 2, 3, 6, 8, 10, 11, 12

▲Up To Search▲

Price & Availability of MAX9171ETA

	To Download MAX9171ETA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .